Method of manufacturing a semiconductor device and semiconductor device obatined with such a method

ABSTRACT

The invention relates to a method of manufacturing a semiconductor device ( 10 ) with a field effect transistor, in which method a semiconductor body ( 1 ) of a semiconductor material is provided, at a surface thereof, with a source region ( 2 ) and a drain region ( 3 ) and with a gate region ( 4 ) between the source region ( 2 ) and the drain region ( 3 ), which gate region comprises a semiconductor region ( 4 A) of a further semiconductor material that is separated from the surface of the semiconductor body ( 1 ) by a gate dielectric ( 5 ), and with spacers ( 6 ) adjacent to the gate region ( 4 ), for forming the source and drain regions ( 2,3 ), in which method the source region ( 2 ) and the drain region ( 3 ) are provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the semiconductor material, and the gate region ( 4 ) is provided with a metal layer ( 7 ) which is used to form a compound ( 8 ) of the metal and the further semiconductor material. The known method in which different metal layers are used to silicidate source and drain regions and gate regions ( 2,3,4 ) has several drawbacks. A method according to the invention is characterized in that before the spacers ( 6 ) are formed, a sacrificial region ( 4 B) of a material that may be selectively etched with respect to the semiconductor region ( 4 A) is deposited on top of the semiconductor region ( 4 A), and after the spacers ( 6 ) have been formed, the sacrificial layer ( 4 B) is removed by etching, and after removal of the sacrificial layer ( 4 B), a single metal layer ( 7 ) is deposited contacting the source, drain and gate regions ( 2,3,4 ). This method is on the one hand very simple as it requires only a single metal layer and few, straight-forward steps and it is compatible with existing (silicon) technology, and on the other hand it results in a (MOS)FET which does not suffer from a depletion layer effect in the fully silicided gate ( 4 ).

The invention relates to a method of manufacturing a semiconductordevice with a field effect transistor, in which method a semiconductorbody of a semiconductor material is provided, at a surface thereof, witha source region and a drain region and with a gate region between thesource region and the drain region, which gate region comprises asemiconductor region of a further semiconductor material that isseparated from the surface of the semiconductor body by a gatedielectric, and with spacers adjacent to the gate region for forming thesource and drain regions, in which method the source region and thedrain region are provided with a metal layer which is used to form acompound of the metal and the semiconductor material, and the drainregion is provided with a further metal layer which is used to form acompound of the metal and the further semiconductor material. The MOSFET(=Metal Oxide Semiconductor Field Effect Transistor) with a polysilicongate obtained by this method may suffer from the problem that adepletion layer effect therein may result in an—unwanted—reduction ofthe effective gate capacitance of the MOSFET and the transistor drivecurrent. This effect has become a significant limitation in CMOS(=Complementary MOS) downscaling. Increasing the doping at the gate-gatedielectric interface can reduce said depletion layer, however gatedoping is limited by the solubility of dopants in poly-silicon.Therefore alternatives to poly-silicon—or amorphous silicon ormonocrystalline silicon—gates have to be found.

A method as mentioned in the opening paragraph is known from U.S. Pat.No. 6,204,103, which was issued on Mar. 20, 2001. Therein such a methodis described in column 6 line 51 to column 7 line 10, in which thesource and the drain of a silicon MOSFET are silicided with one metallayer and the gate is silicided with another metal layer, the lattermetal layer being different for the polysilicon gates of a NMOS and aPMOS transistor. This procedure offers the possibility of avoiding theabove-mentioned depletion effect and thus reduction of the effectivegate capacitance may be avoided.

A drawback of such a method is that it is rather complicated as itcomprises different steps for siliciding source and drain on the onehand and a polysilicon gate on the other hand. Moreover, it containsseveral other steps like a CMP (=Chemical Mechanical Polishing) step,which increase the complexity of the method.

It is therefore an object of the present invention to avoid the abovedrawbacks and to provide a method which is simple and offers thepossibility of avoiding the above mentioned depletion layer effect, inparticular in MOSFETs with a polysilicon gate.

To achieve this, a method of the type described in the opening paragraphis characterized in accordance with the invention in that before thespacers are formed, a sacrificial region of a material that may beselectively etched with respect to the semiconductor region is depositedon top of the semiconductor region, and after the spacers have beenformed, the sacrificial layer is removed by etching, and after removalof the sacrificial layer, a single metal layer is deposited contactingthe source, drain and gate regions. The invention is based, inter alia,on the recognition that full silicidation of a polysilicon gate, bywhich the above-mentioned depletion layer effect is avoided, ispossible. Moreover this may be carried out at the same time as thesilicidation of the source and the drain, provided that the thickness ofthe polysilicon gate is limited to a thickness which is relativelysmall, compared to the standard gate thickness of current processes. Theinvention is further based on the recognition that a reduction of saidthickness is unwanted as the height of a gate stack would decrease,which has large impacts on the technology used, such as on ion implantenergies and spacer thickness. By providing a sacrificial region on thesemiconductor region of a gate stack, the height of the gate stack maybe kept constant while the layer thickness of the semiconductor regionis reduced. The thickness of the sacrificial region is chosen to becomplimentary to the desired reduction of the semiconductor region. Thusthe above impacts on technology are avoided and at the same time themethod according to the invention is relatively simple as merely asingle metal layer is needed for siliciding both the source and drainregions and the gate region. The total height chosen for the gate stackdepends on the technology in question, i.e. on the size of the actualtransistor. As an example, for a standard CMOS process the standardsemiconductor region may be e.g. 100 nm thick. In that case thesemiconductor region may be reduced to e.g. 50 nm while the sacrificialregion is chosen to be also 50 nm.

The sacrificial region may be easily removed before deposition of themetal layer due to the fact that it can be etched selectively relativeto e.g the polysilicon. In this way the height and width of the spacersremain unaffected as they are determined by the total height of thetotal gate stack. The etching of the sacrificial region may be eitherwet or dry.

In summary the advantages of the method according to the invention arethat only slight changes to a standard CMOS process are required, i.e.addition of difficult steps like photolithography and CMP are notrequired, that it results in a fully silicide gate and thus that nodepletion effect occurs during operation of the device. Moreover, thedevice obtained remains—after removal of the spacers—relatively planar,which makes the deposition, patterning and etching of a subsequentpre-metal dielectric layer much easier.

In a preferred embodiment the spacers are formed by depositing a layerof a dielectric material on top of the semiconductor body on which thegate region comprising the semiconductor region and the sacrificialregion is present and by subsequently removing the deposited layer ontop of and on both sides of the gate region by etching. This process issimple and width and height of the spacers depend on the height of thegate stack and the thickness of the dielectric layer deposited.

From the above it is clear that the best results with respect toreduction of the depletion layer effect are obtained if thesemiconductor region, e.g. the polysilicon, is completely consumedduring the formation of the compound of the metal and the furthersemiconductor material.

In a favorable embodiment the formation of the compounds between themetal and the semiconductor material and the metal and the furthersemiconductor material is carried out in two separate heating steps, thefirst heating step resulting in an intermediate compound with a lowercontent of the semiconductor material or the further semiconductormaterial and in the second heating step the intermediate compound beingconverted to the compound having a higher content of the semiconductormaterial or of the further semiconductor material. Thus, in case of asilicon MOST and a Cobalt metal layer, the intermediate compound will bee.g. CoSi while the compound will be CoSi₂. The sheet resistance of thelatter material is considerably smaller than that of the former, whichclearly is an important advantage. Preferably, a part of the metal layerwhich has not reacted to form the intermediate compound is removed byetching between the first and the second heating step.

In another favorable modification a layer of the further semiconductormaterial, i.e. a polysilicon layer in the case of a silicon MOST, isdeposited on the surface of the semiconductor body between the twoheating steps. During the second thermal treatment this layer, which ise.g. 5 to 10 nm thick, acts as a source of silicon for the formation ofe.g. CoSi₂ from the CoSi. Therefore, the deposition of this layerrelieves constraints on the thickness of the poly-silicon consumablegate, i.e. the semiconductor silicon region of the gate. The unreactedpart of e.g. the polysilicon layer is removed after the second heatingstep. This may be done either by a selective dry or wet etch or byoxidation and subsequent removal of the resulting oxide by an etchingagent based on HF.

Preferably the spacers are removed after the formation of the compoundsof the metal and the semiconductor material and of the metal and thefurther semiconductor material. In this way the resulting structureremains relatively planar. In general silicon is the preferred materialfor the semiconductor material and the further semiconductor material,while the intermediate compound and the compound are formed bysilicides. Silicon is presently the most widely and most successfullyused material within the semiconductor industry. A semiconductor devicecomprising a field effect transistor obtained with a method according tothe present invention offers the important advantages already describedin the preceding part of the description.

These and other aspects of the invention will be apparent from andelucidated with reference to the embodiments described hereinafter, tobe read in conjunction with the drawing, in which

FIGS. 1 through 6 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of a method inaccordance with the invention,

FIGS. 7 and 8 are sectional views of a semiconductor device at variousstages in the manufacture of the device by means of a modification ofthe method in accordance with the invention, and

FIG. 9 shows the sheet resistance as a function of the thickness of thesemiconductor region of the gate of a device manufactured by a method inaccordance with the invention.

The figures are diagrammatic and not drawn to scale, the dimensions inthe thickness direction being particularly exaggerated for greaterclarity. Corresponding parts are generally given the same referencenumerals and the same hatching in the various figures.

FIGS. 1 through 6 are sectional views of a semiconductor device atvarious stages in the manufacture of the device by means of a method inaccordance with the invention. The device 10 (see FIG. 1) comprises asemiconductor body 1 which, in this case, is made of silicon but whichmay alternatively be made of another suitable semiconductor material.The basis for the body 1 is a p-type silicon substrate 11 in which ann-type so-called well 12 is formed. In the body 1 isolation regions13—so-called trenches—of silicon dioxide are formed. Subsequently on thesurface of the silicon body 1 a gate oxide 5 is formed by thermaloxidation. Then a semiconductor layer 4A, here a polycrystalline siliconlayer, is formed by CVD (=Chemical Vapor Deposition) on top of which asacrificial layer 4B is deposited also by CVD, which sacrificial layerin this example is of silicon nitride, a material which may beselectively removed from the underlying polycrystalline silicon material4A. A mask 111 is then formed on top of the stack at the location of thegate 4 to be formed.

Subsequently (see FIG. 2) both the silicon nitride layer 4B and thepolycrystalline silicon layer 4A are removed outside the area of themask 111, by which step a gate stack 4 is formed comprising gate oxide5, polycrystalline region 4A and sacrificial region 4B. The thickness ofthe region 4A was chosen to be 40 nm and that of the sacrificial region4B was chosen to be 60 nm. The thickness of the gate stack 4 thus isapproximately equal to 100 nm, which in a standard CMOS processcorresponds to the height for sub 100 nm devices.

Next (see FIG. 3) shallow n-type implantations 2B,3B are made to formthe LDD (=Lightly Doped Drain) extensions of the source and drainregions 2,3 of the MOSFET to be formed. Next a high-energy p-type—socalled HALO—tilted implantation is carried out, which is not separatelyshown in the drawing and which is performed to raise the channel dopingat the LDD edge. Then spacers 6 are formed as follows. A dielectriclayer 6 of silicon dioxide is deposited by means of CVD over the device10. thus covering the gate stack 4. The thickness of the dielectriclayer 6 in this example amounts to 90-100 nm. Then, by means of dryetching, the deposited layer is again removed such that the surface ofthe body 1 at both sides of the gate stack 4 as well as the uppersurface of the sacrificial region 4B are clear. Due to the isotropicnature of the etching, spacers 6 of silicon dioxide remain attached tothe side faces of the gate stack 4. Now deeper n+ type implantations2A,3A are carried out in order to complete the source and drain 2,3formation. The semiconductor body is then annealed at a temperature of1000 to 1100 degree Celsius in order to activate the source and drainimplantations 2A,2B,3A,3B. FIG. 3 shows all these steps in a singlepicture.

Subsequently (see FIG. 4) the sacrificial region 4B of the gate stack 4is removed by selective etching. Etching is done in this example bymeans of wet etching using hot phosphoric acid as an etchant for thesilicon nitride of region 4B In this way the etching is not onlyselective with respect to the polycrystalline region 4A but also withrespect to the silicondioxide of the spacers 6 and a thin thermal oxidewhich may be present on the surface of the semiconductor body 1 on bothsides of the gate stack 4. Next, a metal layer 7 is deposited over thestructure 10. In this example the metal layer 7 comprises a 10 nm thickcobalt layer and a 8 nm thick titanium layer on top thereof. Thefunction of the titanium layer may be to prevent shortcuts after thesilicidation and to act as a barrier for and/or getter of oxygen.

Next (see FIG. 5) the device 10 is thermally treated in order to formsilicided regions 8, i.e. region 8A from a part of the source and drain2,3 and region 8B from the polycrystalline region 4A. In this examplethe formation of silicided regions 8A,8B take place by using two heatingsteps: a first one between 400 and 600° C., here at about 540 degreesCelsius, in which the cobalt layer 7 turns to CoSi. Next the unreactedtitanium and the unreacted cobalt are removed by etching. Then a secondheating step is performed between 600 and 900° C., here at about 850degrees Celsius. In this step the CoSi formed in regions 8 is convertedinto CoSi₂. On the one hand, now the regions 8A have a suitablethickness and on the other hand the polycrystalline region 4A becomesfully silicided region 8B. Thus, a depletion layer effect in the gate 4is avoided.

Finally (see FIG. 6) the spacers 6 are removed by dry etching. Theresulting structure 10 now is (again) relatively planar although theheight of the gate stack 4 in intermediate stages of the manufacture hasbeen considerably larger than the resulting height of the gate 4. Themanufacture of the MOSFET is further completed by deposition of apre-metal dielectric, e.g. silicon dioxide, followed by patterningthereof, deposition of a contact metal layer, e.g. of aluminum, againfollowed by patterning. The latter steps are not shown in the Figure.

FIGS. 7 and 8 are sectional views of a semiconductor device at variousstages in the manufacture of the device by means of a modification ofthe method in accordance with the invention. Most of the steps of themethod correspond to those of the previous example, and for theirdescription reference is made here to the above part of the description.The stages shown in FIGS. 7 and 8 correspond to the stage of FIG. 5 inthe previous example. After the first heating step (see FIG. 7) in whichthe metal layer 7 has reacted with silicon, thereby forming silicideregions 8A,8B comprising CoSi, and after removal of the remainingtitanium and cobalt not taking part in the reaction, a thinpolycrystalline silicon layer 44 is deposited by means of CVD on top ofthe structure 10. The thickness of layer 44 may be in the range of 5 to10 nm. Next (see FIG. 8) the second heating step is performed in whichthe CoSi is converted to CoSi₂. The silicon layer 44 will be at leastpartly consumed in this step and the remainder thereof is removed by anetching step. In this way the requirement of an accurate determinationof the polycrystalline region 4A is mitigated. The importance of anaccurate determination of the thickness of the polycrystalline region 4Ain a method without the steps of the second example can be elucidatedwith reference to FIG. 9.

FIG. 9 shows the sheet resistance as a function of the thickness of thepolycrystalline region of the gate of a device manufactured by a methodin accordance with the invention. Curve 90 which connects measuringpoints 91 shows the sheet resistance (ρ_(sh)) of regions 8 found inthese experiments as a function of the thickness (d) of thepolycrystalline region 4A of the gate 4. Curve 92 corresponds to thesheet resistance of bulk CoSi₂, which is equal to about 8 ohm/square,the sheet resistance of CoSi being higher. Thus, it is clear that, inthis example, the conditions of which correspond to those of the firstembodiment described above, only for a thickness of the region 4A ofabout 40 nm, the desired full conversion to CoSi₂ is realized.

It will be obvious that the invention is not limited to the examplesdescribed herein, and that within the scope of the invention manyvariations and modifications are possible to those skilled in the art.

For example, instead of silicon nitride for the sacrificial region alsoother suitable materials or a combination of materials may be used suchas silicon oxynitride or an alloy of silicon and germanium. The spacerscould (then) be made of a material other than silicondioxide, e.g.silicon nitride. Furthermore, instead of a thermal oxide, a depositedoxide could be used to form the gate dielectric. In a favorablemodification, the gate dielectric comprises silicon nitride, preferablydeposited by CVD, as this material is more stable with respect to thesiliciding process. It is further noted that to form a silicide othermetals may be used instead of cobalt, like titanium or molybdenum. Thesilicidation could be done in a single step. The semiconductor bodycould be made of another semiconductor material such as GaAs orGermanium. In these cases still a polycrystalline or amorphous silicongate could be used.

1. Method of manufacturing a semiconductor device with a field effecttransistor, in which method a semiconductor body of a semiconductormaterial is provided, at a surface thereof, with a source region and adrain region and with a gate region between the source region and thedrain region, which gate region comprises a semiconductor region of afurther semiconductor material that is separated from the surface of thesemiconductor body by a gate dielectric, and with spacers adjacent tothe gate region for forming the source and drain regions, in whichmethod the source region and the drain region are provided with a metallayer which is used to form a compound of the metal and thesemiconductor material, and the gate region is provided with a metallayer which is used to form a compound of the metal and the furthersemiconductor material, characterized in that before the spacers areformed, a sacrificial region of a material that may be selectivelyetched with respect to the semiconductor region is deposited on top ofthe semiconductor region, and after the spacers have been formed, thesacrificial layer is removed by etching, and after removal of thesacrificial layer, a single metal layer is deposited contacting thesource, drain and gate regions.
 2. A method as claimed in claim 1,characterized in that the spacers are formed by depositing a layer of adielectric material on top of the semiconductor body on which the gateregion comprising the semiconductor region and the sacrificial region ispresent and by subsequently removing the deposited layer on top of andon both sides of the gate region by etching.
 3. A method as claimed inclaim 1, characterized in that the semiconductor region is completelyconsumed during the formation of the compound of the metal and thefurther semiconductor material.
 4. A method as claimed in claim 1,characterized in that the formation of the compounds between the metaland the semiconductor material and the metal and the furthersemiconductor material is carried out in two separate heating steps, thefirst heating step resulting in an intermediate compound with a lowcontent of the semiconductor material or of the further semiconductormaterial and in the second heating step the intermediate compound beingconverted to the compound having a higher content of the semiconductormaterial or of the further semiconductor material.
 5. A method asclaimed in claim 4, characterized in that between the two heating steps,a part of the metal layer which has not reacted to form the intermediatecompound is removed by etching.
 6. A method as claimed in claim 4,characterized in that between the two heating steps, a layer of thefurther semiconductor material is deposited on the surface of thesemiconductor body.
 7. A method as claimed in claim 6, characterized inthat after the second heating step, a part of the layer of the furthersemiconductor material which has not reacted to form the compound isremoved by etching.
 8. A method as claimed in claim 1, characterized inthat after the formation of the compounds of the metal and thesemiconductor material and of the metal and the further semiconductormaterial, the spacers (6) are removed.
 9. A method as claimed in claim1, characterized in that for the semiconductor material as well as forthe further semiconductor material silicon is chosen, and for theintermediate compound and for the compound of the metal and thesemiconductor material and the further semiconductor material a metalsilicide is chosen.
 10. A semiconductor device comprising a field effecttransistor obtained by a method as claimed in anyone of the precedingclaims.